Experis
nn Description:nn Debugging regression fails and fixing verification issues or working with designers to fix design bugs.
Assist with silicon observations often requiring replication of behaviors in simulation to root cause.
Developing stimulus with x86 Assembly and/or internal ISA exercisers.
nn Key skills:nn System Verilog and C/C++.
Scripting with Perl or equivalent languages.
Simulation and debug with a Verilog based functional simulator.
Coding in x86 Assembly language.
Strong knowledge of microprocessor architecture (x86 preferred) Experience 3+ years of general functional verification experience with digital designs.
Working experience in UNIX software environment.
nnEducation Requirementsnn Bachelor of Science in EE, CE, or CS with minimum of 7 years of related industry experience OR Masters of Science in EE, CE, or CS with minimum of 5 years of related industry experience